1. Field of the Invention
This invention pertains generally to speed signal detection in serial bus device communication. More particularly, the invention is a method and apparatus for accelerating detection of speed code signals, and in particular S400 signals in IEEE Standard 1394-1995, to thereby reduce the bottleneck through physical layer services of a serial bus device.
2. The Prior Art
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) defines the IEEE Standard 1394-1995 serial bus architecture in the document xe2x80x9cIEEE Standard for a High Performance Serial Busxe2x80x9d published Aug. 30, 1996 which is incorporated herein by reference. In IEEE 1394, the serial bus architecture is defined in terms of nodes. In general, a node is an addressable entity (i.e., a logical entity with a unique address), which can be independently reset and identified.
The IEEE Standard 1394-1995 further describes a set of three stacked layers comprising a transaction layer, a link layer (LINK), and a physical layer (PHY). Interoperability between the serial bus nodes begins with the physical connection, typically through cables, connectors, and PHY silicon.
The PHY has three primary functions: transmission and receptions of data bits, arbitration, and provision for the electrical and mechanical interface. Transmission of data bits is carried out using the transmission format 1 depicted in FIG. 1. The transmission format 1 includes a data prefix 2 and a data packet 3.
For every data packet 3 that is transmitted, the data packet 3 is preceded by a data prefix 2. The data packet 3 may vary in size according to the data transmitted. For example, the data packet may be 8 kilobits (Kb) at S100 speeds (or 32 Kb at S400 speeds).
The data prefix 2 communicates, among other things, a speed code signal to indicate the data rate of transmission. The cable environment supports multiple data rates of 98.304 megabits per second (Mb/s) or S100, 196.608 Mb/s or S200, and 393.216 Mb/s or S400. The lowest speed (S100) is known as the xe2x80x9cbase ratexe2x80x9d. If a higher rate is supported then all lower rates also required.
Speed signaling (also known as common mode signaling) is carried out by indicating an analog signal, and in particular, a common voltage drop (Vcm) across the Twisted Pair B (TPB) interface of the cable media as is known in the art. As noted above, this speed code signal is communicated during the data prefix 2 portion of the data transmission 1. In general, the speed code signal communicated during the data prefix 2 must be completed 40 nanoseconds (ns) before the data packet 3 portion.
FIG. 2a and FIG. 2b illustrate generally speed code signals communicated by the PHY devices as described above. FIG. 2a illustrates an S200 speed code signal 4 to indicate the S200 data rate. FIG. 2b illustrates an S400 speed code signal 5 to indicate the S400 data rate. The base rate (S100) is indicated by a lack or absence of a speed signal code signal during the data prefix 2.
The S200 speed code signal 4 and the S400 speed code signal 5 are generally 100 ns in length. However, the S200 speed code signal 4 indicates a Vcm drop of about 140 millivolts (mV). In contrast, the S400 speed code signal 5 indicates a Vcm drop of about 450 mV. The details of implementing speed signal reception was largely left to the designer of a PHY to provide the necessary filtering algorithm that ascertains the various speed code signals communicated by the other PHY devices on the serial bus.
Referring now to FIG. 3 there is generally shown a xe2x80x9cdriver blastxe2x80x9d signal 6 which may sometimes be indicated during the data prefix portion 2 of the data transmission 1. This driver blast signal 6 may sometimes arise when the output of differential port drivers are not activated simultaneously, thereby creating a Vcm drop of about 140 mV generally lasting no more than 10 ns.
The problem created by the driver blast signal 6 is that the Vcm drop of the driver blast signal 6 appears like and has a similar slope and amplitude to the Vcm drop of an S200 speed code signal 4. The difference between the two signals is the length of the signal, the S200 speed code signal 4 lasting about 100 ns while the driver blast signal 6 generally lasting no longer than 10 ns. To distinguish between the driver blast signal 6 and the speed code signals 4, 5, and to avoid misinterpreting the driver blast signal 6 for a speed code signal, a proposed speed filter algorithm has been provided in Table 8-21 of the P1394a Draft 4.0 (most recent), published by the IEEE in Sep. 15, 1999 and is incorporated herein by reference. Many current PHY devices implement this speed filter algorithm.
This proposed speed filter algorithm is represented in flow chart form in FIG. 4. In general, signals are sampled at 20 ns intervals. According to the algorithm, if two consecutive S200 signals (i.e., Vcm drop level to that of an S200 speed code signal) are observed then S200 mode is determined to be valid. Similarly, if two consecutive S400 signals are observed, then S400 mode is determined to be valid. Otherwise S100 mode is the default mode. By requiring two consecutive signals, both of S200 or both of S400, the driver blast signal 6 can be filtered out because two consecutive samples requires the necessary Vcm signal for a 20 ns period minimum, whereas the Vcm produced by the driver blast signal 6 generally lasts no more than 10 ns.
As shown in FIG. 4, it is common to first detect the S200 signal 4 before detecting the S400 signal 5, primarily due to the slope of the S400 signal. This is because the leading edge of an S400 speed signal is a somewhat leisurely drop to S400 levels; it spends considerable time transitioning through S200 range. In general, the total propagation delay (bottleneck) of a signal through a PHY device is generally 130 to 140 ns, a portion of which is dedicated to sampling speed codes. For detection of S400 speed signals for example, the prior art algorithm described above may not determine the validity of an S400 speed signal until as late as 60 ns (20 ns for sampling the S200 signal, plus 40 ns for sampling two consecutive S400 signals). It is noted that for detection of S200 speed signals, the prior art algorithm described above consumes about 40 ns (two consecutive samples at 20 ns each) for sampling signal. Thus, the propagation delay for detecting S400 signals will generally be greater than the propagation delay for detecting S200 signal.
It is observed that the Vcm drop level produced by the driver blast 6 does not reach the Vcm drop level produced by an S400 speed code signal 5. Thus, for S400 speed code signaling, filtering for driver blast 6 is not generally required. The prior art algorithm which samples and filters for two consecutive S400 signals thus increases the propagation delay through a PHY device, increasing the overall propagation delay of an S400 transmission on the serial bus as noted above.
Additionally, according to the prior art algorithm, the port must already be receiving RX_DATA_PREFIX. Thus portRspeed cannot go valid (a speed mode cannot be validated) until one clock after portRxe2x80x94typically a 20 ns delay.
Accordingly, there is a need for a method and apparatus for accelerating detection of speed code signals to thereby reduce the bottleneck through a PHY device due to speed signal sampling. The present invention satisfies these needs, as well as others, and generally overcomes the deficiencies found in the background art.
An object of the invention is to provide a method and apparatus for accelerating detection of speed code signals which overcomes the deficiencies of the prior art.
Another object of the invention is to provide a method and apparatus for accelerating detection of speed code signals which reduces the propagation through a PHY device.
Another object of the invention is to provide a method and apparatus for accelerating detection of S400 speed code signals.
Further objects and advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing the preferred embodiment of the invention without placing limitations thereon.
The present invention is a method and apparatus embodied in physical layer services suitable for use with serial bus devices, such as IEEE standard 1394-1995 serial bus devices. The invention further relates to machine readable media on which are stored embodiments of the present invention. It is contemplated that any media suitable for retrieving instructions is within the scope of the present invention. By way of example, such media may take the form of magnetic, optical, or semiconductor media. More particularly, a first embodiment of the present invention comprises speed code algorithm code in the form of HDL (Hardware Description Language) code. Another embodiment of the present invention comprises silicon devices (e.g., state machine logic) carrying out the functions described herein with respect to the speed code algorithm.
In its most general terms, the algorithm of the present invention comprises validating S400 mode immediately after detecting an S400 speed signal level, or after detecting an S400 speed signal level following a first S200 speed signal. The invention further provides S200 and S100 mode validation according to current implementations.
More particularly, the speed code algorithm samples signals to detect speed codes signals which are transmitted in the data prefix portion 2 of the data transmission format 1 as described above in conjunction with FIG. 1. In a preferred embodiment, signals are sampled at 20 ns intervals.
The present invention does not have RX_DATA_PREFIX as a prerequisite for speed signal detection. Instead it relies on clearing speed signal registers at approximate times (e.g., at end of packets, chip resets, end of self-id speed signal trap operations). According to this arrangement, speed signaling is available to the state machine logic earlier thereby reducing PHY propagation delay.
The speed code algorithm ascertains or otherwise detects a first speed code signal of either S200 or S400. In a first case, a first S200 speed code signal is detected as the first speed code signal. The algorithm determines whether the next sampled signal is an S400 speed code signal. If so, the algorithm validates the S400 mode immediately based on the consecutive S200 and S400 signals. If not, the algorithm determines if the sampled signal is a second S200 speed code signal. If so, the algorithm validates S200 mode based on the two consecutive S200 signals. Otherwise, the algorithm does not validate either S200 or S400 mode based on the sampled signals detected.
In a second case, a first S400 speed code signal is detected as the first speed code signal, rather than an S200 speed code. The algorithm validates the S400 mode immediately based on the detection of the S400 signal since there is no other mechanism for producing a common mode excursion (Vcm level) in the S400 range, as noted above.
Viewed from one vantage point, the method of the present invention comprises detecting a first S200 speed signal, detecting a first S400 speed signal immediately after detecting the first S200 speed signal; and validating S400 speed mode immediately after detecting the first S400 speed signal.
Viewed from another vantage point, the method of the present invention comprises detecting a first S400 speed signal as the first speed code signal; and validating S400 speed mode immediately after detecting the first S400 speed signal.